1. Field
Example embodiments relate to a semiconductor memory device, for example, a semiconductor memory device including a memory array having a floating body transistor using operation of a bipolar junction transistor.
2. Description of Related Art
A layout area of a semiconductor memory device may be reduced using a transistor having a floating body (hereinafter, a floating body transistor). The floating body transistor stores majority carriers in the floating body. However, since the stored majority carriers are lost in a known amount of time, the floating body transistor requires refreshing.
A memory cell array including a dynamic memory cell has been developed that has a floating body transistor using the operation of a bipolar junction transistor to improve an operating speed and a data retention characteristic.
FIG. 1 is an example circuit diagram of a floating body transistor.
Referring to FIG. 1, the floating body transistor includes an NMOS field effect transistor (hereinafter, referred to as ‘NMOS transistor’) NMOS and an NPN bipolar junction transistor (hereinafter, referred to as ‘NPN transistor’) NPN. A source S of the NMOS transistor NMOS also functions as an emitter E of the NPN transistor NPN, a drain D of the NMOS transistor NMOS also functions as a collector C of the NPN transistor NPN, and a base B of the NPN transistor NPN is electrically floating. Also, a coupling capacitor CC is located between a gate G of the NMOS transistor NMOS and the base B of the NPN transistor NPN.
Data “1” refers to a state where majority carriers (holes, for example) are accumulated in a floating body region, while the data “0” refers to a state where minority carriers (electrons, for example) are accumulated in the floating body region.
When a gate voltage Vg is 0V, current rapidly rises before a drain-source voltage Vds reaches a known voltage level, irrespective of whether the floating body transistor is in a data “1” state or a data “0” state. Thereafter, when the drain-source voltage Vds reaches the known voltage level or higher, holes are initially injected into the base B of the NPN transistor NPN due to drain coupling so that an electrical potential of the base B increases. As a result, a forward voltage is applied between the base B and the emitter E causing an emitter current to flow. The emitter current is supplied to the collector C, and the passage of emitter current through a band-bending region between the base B and the collector C causes band-to-band tunneling and/or impact ionization.
Due to the band-to-band tunneling and/or impact ionization, holes are injected from the collector C to the base B and the electrical potential of the base B further increases. As a result, the drain-source voltage Vds increases, so that when the NPN transistor NPN is turned on, a bipolar current Ids rapidly rises due to a feed forward system of the NPN transistor NPN. Impact ionization causes a multiplication factor to increase, resulting in a further rise in bipolar current Ids.
The data “1” state is written due to the bipolar current Ids. When the floating body transistor is in the data “1” state, the NPN transistor NPN is turned on at a lower drain-source voltage Vds as compared with the case of the data “0” state, thereby increasing the bipolar current Ids. This is because band-to-band tunneling and/or impact ionization causes a higher number of holes to accumulate in the floating body resulting in a higher electric potential of the floating body and the NPN transistor NPN can be quickly turned on, compared to when the floating body transistor is in the data “0” state.
When the gate voltage Vg is negative, the bipolar current Ids rapidly increases at a relatively high drain-source voltage Vds as compared to the case where the gate voltage Vg is 0V. As the gate voltage Vg decreases, an electrostatic potential of the base B decreases. Therefore, it is necessary to increase the drain-source voltage Vds to turn on the NPN transistor NPN due to band-to-band tunneling and/or impact ionization.